VIS & VL2MV

18/01/2016:
-----------

    Installing VIS model checker
    ----------------------------

        Download from: http://vlsi.colorado.edu/~vis/vis_files_2.4.html

        Note: First do the installation of glu and then install vis or vl2mv (order doesn't matter)

        Installation: Follow the steps in the VIS README file in http://vlsi.colorado.edu/~vis/vis_files_2.4.html

        Pitfalls: Dont extract the vis and glu .tar.gz files using gui. Instead use the commands given below
            % gzip -dc /tmp/glu-2.4.tar.gz | tar xf -
            % gzip -dc /tmp/vis-2.4.tar.gz | tar xf -

        Setting environment for VIS
            set VIS_LIBRARY_PATH=$cwd/share

    Installing vl2mv:
    ----------------

        Follow instructions in the README file in http://vlsi.colorado.edu/~vis/vis_files_2.4.html

        "make check" will fail since the vl2mv-2.4/examples folder is empty. Don't worry about that

VIM

* Changing the tab width to 4 spaces permanenlty
    Add the following to .vimrc (create one if not found in ~/)
        filetype plugin indent on
        " show existing tab with 4 spaces width
        set tabstop=4
        " when indenting with '>', use 4 spaces width
        set shiftwidth=4
        " On pressing tab, insert 4 spaces
        set expandtab
    Ref: http://stackoverflow.com/questions/234564/tab-key-4-spaces-and-auto-indent-after-curly-braces-in-vim 

Indenting a block of codes in Vim
    V j j >
    Ref: http://stackoverflow.com/questions/235839/indent-multiple-lines-quickly-in-vi     

SCREEN

Start: screen -S "Session name"
New window: C-a C-c
Switch windows: C-a C-a
Name a screen: C-a Shift-a
List screen windows: C-a w
Detach screen: C-a d
Detach screen: screen -d
Detach screen from elsewhere and attach it here : screen -d -r "Session id"
List all detached sessions: screen -list
And the obvious thing to do if you are stuck: man screen

PYTHON

26/10/15:
---------

* CLASSES AND METHODS:
----------------------

* Possible conventions include capitalizing method names, prefixing data attribute names with a small unique string (perhaps just an underscore), or using verbs for methods and nouns for data attributes.

*  It is not necessary that the function definition is textually enclosed in the class definition: assigning a function object to a local variable in the class is also ok
# Function defined outside the class
def f1(self, x, y):
    return min(x, x+y)
class C:
    f = f1
    def g(self):
        return 'hello world'
    h = g

* Methods may call other methods by using method attributes of the self argument:
class Bag:
    def __init__(self):
        self.data = []
    def add(self, x):
        self.data.append(x)
    def addtwice(self, x):
        self.add(x)
        self.add(x)

* The syntax for a derived class definition looks like this:
class DerivedClassName(BaseClassName):
    <statement-1>
    .
    .
    .
    <statement-N>

* when the base class is defined in another module:
class DerivedClassName(modname.BaseClassName):

* A method of a base class that calls another method defined in the same base class may end up calling a method of a derived class that overrides it

* There is a simple way to call the base class method directly: just call BaseClassName.methodname(self, arguments).

* There is a convention that is followed by most Python code: a name prefixed with an underscore (e.g. _spam) should be treated as a non-public part of the API (whether it is a function, a method or a data member).

* Any identifier of the form __spam (at least two leading underscores, at most one trailing underscore) is textually replaced with _classname__spam, where classname is the current class name with leading underscore(s) stripped.

* Useful for Verilog parsing:
A piece of Python code that expects a particular abstract data type can often be passed a class that emulates the methods of that data type instead. For instance, if you have a function that formats some data from a file object, you can define a class with methods read() and readline() that get the data from a string buffer instead, and pass it as an argument.

* PYTHON STYLE GUIDE:
---------------------
* https://www.python.org/dev/peps/pep-0008/

MODELSIM

View schematic of a VHDL file in Modelsim
    * Go to SIM tab in the panel after simulation
    * Right click on the top module name and ADD -> TO SCHEMATIC -> SELECTED REGION
    * Go to SCHEMATIC tab
        * Drag and select all items in the region
        * Right click on it
        * EXPAND NET TO -> DESIGN INPUTS       

ICARUS Verilog

Installation:
------------
Installation guide: http://iverilog.wikia.com/wiki/Installation_Guide

Download the latest one from git
    https://github.com/steveicarus/iverilog

Trying out the first example
    Use the following command to generate .vcd file
        iverilog -o example_3_1.vvp example_3_1_tb.v
    Display the waveforms
        export DISPLAY=:0.0
        gtkwave example_3_1.vcd

GIT

git add -u before committing the changes after you delete a file in the git directory